1 radiation hardened bicmos dual spdt analog switch HS-303CEH the HS-303CEH is an analog sw itch and a monolithic device that is fabricated using intersil?s dielectrically isolated radiation hardened silicon gate (rsg) process technology to insure latch-up free operation. it is pinout compatible and functionally equivalent to the hs-303rh. this switch offers low-resistance switching perfor mance for analog voltages up to the supply rails. on-resistance is low and stays reasonably constant over the full range of operating voltage and current. on-resistance also stays reasonab ly constant when exposed to radiation. break-before-make switching is controlled by 5v digital inputs. the HS-303CEH ca n operate with rails of 15v. specifications the detailed electrical specifications for the HS-303CEH is contained in smd 5962-95813 . a ?hot-link? is provided from our website for downloading. features ? qml, per mil-prf-38535 ? no latch-up, dielectrically isolated device islands ? pinout and functionally compatible with intersil hs-303rh series analog switches ? analog signal range equal to the supply voltage range ? low leakage . . . . . . . . . . . . . . . . . . . . . 150na (max, post-rad) ?low r on . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 (max, post-rad) ? low standby supply current . . . . . . . 150a (max, post-rad) ? radiation assurance - high dose rate (50 to 300rad(si)/s) . . . . . . . . 100krad(si) - low dose rate (0.01rad(si)/s) . . . . . . . . . . . . . 50krad(si)* ? single event effects - for let = 60mev-mg/cm 2 at 60 incident angle, <150pc charge transferred to the output of an off switch * product capability established by initial characterization. the eh version is acceptance tested on a wafer-by-wafer basis to 50krad(si) at low dose rate. figure 2. recommended operating area in grey n p in d s figure 1. logic circuit table 1. truth table logic sw1 and sw2 sw3 and sw4 0offon 1onoff 0 2 4 6 8 10 12 14 16 10 11 12 13 14 15 negative switch voltage (v sw- ) negative supply voltage (v ee- ) caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. december 19, 2013 fn8399.2
HS-303CEH 2 fn8399.2 december 19, 2013 pin configuration HS-303CEH (14 ld flatpack) top view nc gnd in1 s3 d3 d1 s1 v+ v- s4 d4 d2 in2 s2 14 13 12 11 10 9 8 2 3 4 5 6 7 1 pin descriptions pin number pin name pin description 1 nc not electrically connected 2 s3 analog switch: source connection 3 d3 analog switch: drain connection 4 d1 analog switch: drain connection 5 s1 analog switch: source connection 6 in1 digital control input for sw1 and sw3 7gndground 8 v- negative power supply 9 in2 digital control input for sw2 and sw4 10 s2 analog switch: source connection 11 d2 analog switch: drain connection 12 d4 analog switch: drain connection 13 s4 analog switch: source connection 14 v+ positive power supply ordering information order number part number temp. range (c) package (rohs compliant) pkg. dwg. # 5962r9581308vxc hs9-303ceh-q -55 to +125 14 ld flatpack k14.a 5962r9581308v9a hs0-303ceh-q -55 to +125 die n/a hs9-303ceh/proto hs9-303ceh/proto -55 to +125 14 ld flatpack k14.a hs0-303ceh/sample hs0-303ceh/sample -55 to +125 die n/a note: these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant a nd compatible with both snpb and pb-free soldering operations.
HS-303CEH 3 fn8399.2 december 19, 2013 absolute maximum rating s thermal information voltage between v+ and v- terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . 35v v supply to ground (v+, v-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17.5v analog input voltage (+v s ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+v supply +1.5v (-v s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -v supply -1.5v digital input voltage (+v a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +v supply +4v (-v a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -v supply -4v peak current (s or d) (pulse at 1ms, 10% duty cycle max) . . . . . . . . . . . . . . . . . . . . . . . . 40ma continuous current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kv thermal resistance (typical) ja (c/w) jc (c/w) flatpack package (notes 1, 2) . . . . . . . . . . 105 17 package power dissipation at 125c flatpack package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.48w/c lead temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions operating temperature range . . . . . . . . . . . . . . . . . . . . . .-55c to +125c operating supply voltage range (v supply ) . . . . . . . . . . . . . . . . . . . . 15v analog input voltage (v s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v supply logic low level (v al ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v to 0.8v logic high level (v ah ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.0v to +v supply caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured with the component mounted on a low effective thermal conductivity test board in free air. see tech brief tb379 for details. 2. for jc , the ?case temp? location is the center of the package underside. electrical specifications v supply = 15v unless otherwise specified. boldface limits apply across the operating temperature range, -55c to +125c . symbol parameter test conditions min (note 5) typ max (note 5) units +r ds(on) ?switch on? resistance v d = 10v, i s = -10ma 35 75 ? -r ds(on) ?switch on? resistance v d = -10v, i s = 10ma 35 75 ? +i s(off) leakage current into source of an ?off? switch v s = +14v, v d = -14v -150 0.05 150 na v s = +15v, v d = -15v -20 20 a -i s(off) leakage current into source of an ?off? switch v s = -14v, v d = +14v -150 0.5 150 na v s = -15v, v d = +15v -20 20 a +i d(off) leakage current into drain of an ?off? switch v s = +14v, v d = -14v -150 0.05 150 na v s = +15v, v d = -15v -20 20 a -i d(off) leakage current into drain of an ?off? switch v s = -14v, v d = +14v -150 0.5 150 na v s = -15v, v d = +15v -20 20 a +i d(on) leakage current from an ?on? driver into the switch (drain and source) v s = +14v, v d = +14v -100 -0.1 100 na -i d(on) leakage current from an ?on? driver into the switch (drain and source) v s = -14v, v d = -14v -100 0.01 100 na i al low level input address current all channels v a = 0.8v -1000 0.03 1000 na i ah high level input address current all channels v a = 4.0v -1000 0.03 1000 na i+ positive supply current all channels v a = 0.8v 45 150 a v a1 = 0v, v a2 = 4v v a1 = 4v, v a2 = 0v 0.15 0.6 ma i- negative supply current all channels v a = 0.8v -0.1 -100 a v a1 = 0v, v a2 = 4v v a1 = 4v, v a2 = 0v -0.1 -100 a cis(off) switch input capacitance f rom source to gnd (notes 3, 4) 28 pf cc1 driver input capacitance v a = 0v (notes 3, 4) 10 pf
HS-303CEH 4 fn8399.2 december 19, 2013 cc2 driver input capacitance v a = 15v (notes 3, 4) 10 pf cos switch output measured drain to gnd (notes 3, 4) 28 pf v iso off isolation v gen = 1v p-p , f = 1mhz (notes 3, 4) 40 db v cr cross talk v gen = 1v p-p , f = 1mhz (notes 3, 4) 40 db v cte charge transfer error v s = gnd, c l = 0.01f (notes 3, 4) 15 mv t open break-before-make time delay r l = 300 ? , v s = 3v, v ah = 5v, v al = 0v 10 50 300 ns t on switch turn ?on? time r l = 300 ? , v s = 3v, v ah = 4v, v al = 0v 250 500 ns t off switch turn ?off? time r l = 300 ? , v s = 3v, v ah = 4v, v al = 0v 200 450 ns notes: 3. limits established by characteriza tion and are not production tested. 4. val = 0v and vah = 4v. 5. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. post radiation characteristics v supply = 15v unless otherwise specified. this data is typical test data post radiation exposure at a rate of 50 to 300rad(si)/s. this data is intended to show typica l parameter shifts due to total ionizing dose (high dose radiat ion) t a = +25c. symbol parameter test conditions 0k 100k units +r ds(on) ?switch on? resistance v d = 10v, i s = -10ma 34 35 ? -r ds(on) ?switch on? resistance v d = -10v, i s = 10ma 28 29 ? +i s(off) leakage current into source of an ?off? switch v s = +14v, v d = -14v -0.20 -0.31 na v s = +15v, v d = -15v -0.003 -0.47 a -i s(off) leakage current into source of an ?off? switch v s = -14v, v d = +14v 0.30 0.84 na v s = -15v, v d = +15v 0.001 0.02 a +i d(off) leakage current into drain of an ?off? switch v s = +14v, v d = -14v -1.20 -0.90 na v s = +15v, v d = -15v -0.001 -0.001 a -i d(off) leakage current into drain of an ?off? switch v s = -14v, v d = +14v 0.31 0.90 na v s = -15v, v d = +15v 0.0003 0.001 a +i d(on) leakage current from an ?on? driver into the switch (drain and source) v s = +14v, v d = +14v -0.2 -0.55 na -i d(on) leakage current from an ?on? driver into the switch (drain and source) v s = -14v, v d = -14v 0.15 0.28 na i al low level input address current all channels v a = 0.8v 0.35 0.25 na i ah high level input address current all channels v a = 4.0v 1.98 1.47 na i+ positive supply current all channels v a = 0.8v 55 53 a v a1 = 0v, v a2 = 4v v a1 = 4v, v a2 = 0v 167.2 113.7 a i- negative supply current all channels v a = 0.8v -0.01 -0.01 a v a1 = 0v, v a2 = 4v v a1 = 4v, v a2 = 0v -0.01 -0.02 a t open break-before-make time delay r l = 300 ? , v s = 3v, v ah = 5v, v al = 0v 42 47 ns t on switch turn ?on? time r l = 300 ? , v s = 3v, v ah = 4v, v al = 0v 224 213 ns t off switch turn ?off? time r l = 300 ? , v s = 3v, v ah = 4v, v al = 0v 192 173 ns electrical specifications v supply = 15v unless otherwise specified. boldface limits apply across the operating temperature range, -55c to +125c . (continued) symbol parameter test conditions min (note 5) typ max (note 5) units
HS-303CEH 5 fn8399.2 december 19, 2013 post radiation characteristics v supply = 15v unless otherwise specified. this data is typical test data post radiation exposure at a rate of <10mrad(si)/s. this data is intended to show typical parameter shifts due to total ionizing dose (low dose radiati on). t a = +25c. symbol parameter test conditions 0k 25k 50k 75k 100k units +r ds(on) ?switch on? resistance v d = 10v, i s = -10ma 33.57 34.39 34.37 34.75 34.65 ? -r ds(on) ?switch on? resistance v d = -10v, i s = 10ma 27.56 28.37 28.48 28.92 28.77 ? +i s(off) leakage current into source of an ?off? switch v s = +14v, v d = -14v -0.30 -0.26 -0.36 -0.55 -0.47 na v s = +15v, v d = -15v -0.006 -0.002 -0.002 -0.003 -0.002 a -i s(off) leakage current into source of an ?off? switch v s = -14v, v d = +14v 0.32 0.45 0.75 1.05 0.94 na v s = -15v, v d = +15v 0.004 0.003 0.003 0.003 0.002 a +i d(off) leakage current into drain of an ?off? switch v s = +14v, v d = -14v -0.36 -0.22 -0.25 -0.46 -0.40 na v s = +15v, v d = -15v -0.001 -0.001 -0.001 -0.001 -0.002 a -i d(off) leakage current into drain of an ?off? switch v s = -14v, v d = +14v 0.34 0.43 0.69 1.02 0.92 na v s = -15v, v d = +15v 0.0004 0.0008 0.0011 0.0014 0.0018 a +i d(on) leakage current from an ?on? driver into the switch (drain and source) v s = +14v, v d = +14v -0.25 -0.26 -0.36 -0.55 -0.65 na -i d(on) leakage current from an ?on? driver into the switch (drain and source) v s = -14v, v d = -14v 0.17 0.15 0.26 0.45 0.40 na i al low level input address current all channels v a = 0.8v 0.19 0.30 0.23 0.71 0.48 na i ah high level input address current all channels v a = 4.0v 1.72 0.87 0.83 0.28 1.31 na i+ positive supply current all channels v a = 0.8v 54 51 50 49 50 a v a1 = 0v, v a2 = 4v v a1 = 4v, v a2 = 0v 185 146 129 116 106 a i- negative supply current all channels v a = 0.8v -0.011 -0.015 -0.011 -0.019 -0.022 a v a1 = 0v, v a2 = 4v v a1 = 4v, v a2 = 0v -0.013 -0.016 -0.017 -0.019 -0.014 a t open break-before-make time delay r l = 300 ? , v s = 3v, v ah = 5v, v al = 0v 42.58 50.84 55.63 56.74 58.06 ns t on switch turn ?on? time r l = 300 ? , v s = 3v, v ah = 4v, v al = 0v 221.03 229.24 240.85 249.79 256.37 ns t off switch turn ?off? time r l = 300 ? , v s = 3v, v ah = 4v, v al = 0v 188.62 184.65 182.27 184.06 182.45 ns
HS-303CEH 6 fn8399.2 december 19, 2013 figure 3. switching test circuit figure 4. switching test circuit waveform figure 5. break-before-make test circuit figur e 6. break-before-make test circuit waveforms 15 300 500 450 33 boldface limits apply over the temperature range -55c to 125c symbol parameter test conditions min typ max units truth table logic sw1 and sw2 sw3 and sw4 15 300 500 450 33 boldface limits apply over the temperature range -55c to 125c symbol parameter test conditions min typ max units truth table logic sw1 and sw2 sw3 and sw4
HS-303CEH 7 fn8399.2 december 19, 2013 die characteristics die dimensions: 2815m x 5325m (106 milsx205 mils) thickness: 483m 25.4m (19 mils 1 mil) interface materials: glassivation: type: psg (phosphorous silicon glass) thickness: 8.0k? 1.0k? top metallization: type: alsicu thickness: 16.0k? 2k? substrate: radiation hardened silicon gate, dielectric isolation backside finish: silicon assembly related information: substrate potential: unbiased (di) additional information: worst case current density: <2.0 x 10 5 a/cm 2 transistor count: 216 package lid potential: floating metallization mask layout HS-303CEH d3 d1 s1 in1 gnd d4 d2 s2 in2 s3 v+ s4 v- d1 origin
HS-303CEH 8 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8399.2 december 19, 2013 for additional products, see www.intersil.com/product_tree layout characteristics step and repeat: 2815m x 5325m table 2. layout x-y coordinates pad name x ( m) y ( m) dx ( m) dy ( m) s3 0 4672.5 109 109 d3 -4.5 3861 109 109 d1 -4.5 1314 109 109 s1 0 617.5 109 109 in1 0 0 109 109 gnd 878 0 109 109 vee 1246 0 109 109 in2 2124 0 109 109 s2 2124 617.5 109 109 d2 2128.5 1314 109 109 d4 2128.5 3861 109 109 s4 2124 4672 109 109 vcc 1062 4675 109 109 note: "origin" as labeled in the metallization mask layout is the centroid of the pad labeled "in1".
HS-303CEH 9 fn8399.2 december 19, 2013 about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change december 19, 2013 fn8399.2 added esd ratings to abs max table on page 3 april 5, 2013 fn8399.1 title on page 1 changed cmos to bicmos continuous current in ?absolute maximum ratings? on page 3 changed from 30ma to 10ma ?post radiation characteristics? on page 4 changed unit in positive supply current from ma to a. march 26, 2013 updated throughout 300krad to 100krad. updated ordering information on page 2 updated electrical spec table min and max values fo r leakage current in source and drain for 15v from 5 to 20 updated in post radiation characteristics typical values on page 4 for positive supply current for va1, va2 from 107.1 to 113.7 and negative supply current for va1, va2 from -0.01 to -0.02 added 100k column to post radiat ion characteristics table on page 5 removed negative symbol under 75k column ial, iah fr om 0.71, 0.28 and added negative symbol in i- to 0.019 in va1, va2 removed the words exposed pad from tjc note. updated numbers in table 2 in x(m) column. added note to table 2. december 21, 2012 fn8399.0 initial release
HS-303CEH 10 fn8399.2 december 19, 2013 ceramic metal seal fl atpack packages (flatpack) notes: 1. index area: a notch or a pin one id entification mark shall be located adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identific ation shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. this dimension allows for off-cent er lid, meniscus, and glass over- run. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. the maximum limits of lead dimensions b and c or m s hall be measured at the centroid of the finished lead surfaces, when sol der dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric materi- als shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the me- niscus) of the lead from the body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l d a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m k14.a mil-std-1835 cdfp3-f14 (f-2a, configuration b) 14 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.390 - 9.91 3 e 0.235 0.260 5.97 6.60 - e1 -0.290-7.11 3 e2 0.125 - 3.18 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.270 0.370 6.86 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 - 6 m - 0.0015 - 0.04 - n14 14- rev. 0 5/18/94
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